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[DSP program] TMS320C54x DSP 的cpu和外围设备

Description: 针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行了研究，给了了将乘法化为查表的DA算法，并采用这一算法设计了FIR滤波器。通过FPGA仿零点验证，证明了这一方法是可行和高效的，其实现的滤波器的性能优于用DSP和传统方法实现FIR滤波器。最后介绍整数的CSD表示和还处于研究阶段的根据FPGA实现的要求改进的最优表示。-view of the FPGA FIR filters achieve the key-- the multiplication Efficient Implementation of research, to the multiplication of the DA into Lookup algorithm, and using the algorithm design of the FIR filter. FPGA through imitation 0.1 certification proves that the method is feasible and efficient, achieve superior filter performance DSP and traditional FIR filter method. Finally, integral and said the CSD is still in the research stage on the basis of FPGA requirements of the optimal said.
Platform: | Size: 1424384 | Author: 呈一 | Hits:

[VHDL-FPGA-Verilog] Pall_FIR

Description: FIR低通滤波器得设计，采用并行算法设计-FIR low-pass filter was designed in parallel algorithm design
Platform: | Size: 2004992 | Author: luyingc | Hits:

[VHDL-FPGA-Verilog] fir

Description: 我自己用VHDL语言编的16阶FIR数字滤波器，仿真是在Quartus II上通过的，对大家一定有帮助的，压缩文件里还有详细的设计说明呢，肯定让你完全了解数字滤波器的设计。-VHDL language with my own series of 16-order FIR digital filter in the Quartus II simulation is adopted, the U.S. will certainly be helpful, compressed document also detailed design description, it certainly allows you to fully understand the digital filter设计.
Platform: | Size: 909312 | Author: 王志 | Hits:

[Other] VerilogHDL

Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
Platform: | Size: 79872 | Author: sundan | Hits:

[VHDL-FPGA-Verilog] fir_parall

Description: 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), through the verification.
Platform: | Size: 3072 | Author: 张堃 | Hits:

[VHDL-FPGA-Verilog] halfband

Description: verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。-verilog halfband FIR
Platform: | Size: 1024 | Author: lv | Hits:

[Other] FIR

Description: This implementation of Low power Finite Impulse response filter design and implemented in Verilog-This is implementation of Low power Finite Impulse response filter design and implemented in Verilog
Platform: | Size: 5120 | Author: Ravindra | Hits:

[Books] fir

Description: 本文以软件无线电为指导，提出基于CORDIC算法利用FPGA平台数字下变频器设计方案。首先分析下变频器的结构；然后采用模块化设计思想，将数字下变 频的功能模块包括数字控制振荡器、CIC抽取滤波、HBF抽取滤波器、FIR低通滤波器进行分析和FPGA的设计；最后在 MATLAB/DSPBuilder下硬件仿真模块进行仿真并给出仿真结果。-In this paper, software-defined radio as the guidance, based on the CORDIC algorithm uses the FPGA platform, digital down-converter design. First analyzes the structure of down-converter and then use a modular design concept, the digital down-conversion function modules including digital controlled oscillator, CIC decimation filtering, HBF decimation filter, FIR low-pass filter for analysis and FPGA design the final In the MATLAB/DSPBuilder under the hardware emulation module simulation and simulation results.
Platform: | Size: 201728 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] fir

Description: 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information in the hope that we can use this code for an honest to improve their skills.
Platform: | Size: 3322880 | Author: de de | Hits:

[VHDL-FPGA-Verilog] robust_fir_latest.tar

Description: RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 different architectures, parallel, serial or something in the middle (named Nserial). The architecture is determined according to the MACNUM parameter (multiplayer-accumulator). The RobustVerilog top source file is fir.v. The command line calls it with an additional definition file named def_fir_top.txt The default definition file def_fir_top.txt generates 3 filters, 1 parallel, 1 serial and 1 Nserial. Changing the interconnect parameters should be made only in def_fir_top.txt in the src/base directory (changing multiplier number, filter order etc.).-RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 different architectures, parallel, serial or something in the middle (named Nserial). The architecture is determined according to the MACNUM parameter (multiplayer-accumulator). The RobustVerilog top source file is fir.v. The command line calls it with an additional definition file named def_fir_top.txt The default definition file def_fir_top.txt generates 3 filters, 1 parallel, 1 serial and 1 Nserial. Changing the interconnect parameters should be made only in def_fir_top.txt in the src/base directory (changing multiplier number, filter order etc.).
Platform: | Size: 6144 | Author: 尤恺元 | Hits:

[Graph program] filter_dds_10.29_7.2

Description: 一个经过处理的FIR filter, verilog HDL实现在FPGA上-One new design of digital FIR filter , which can be implemented in FPGA kit
Platform: | Size: 1033216 | Author: chen | Hits:

[VHDL-FPGA-Verilog] 20140825

Description: FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code of the filter, presented here we commonly used serial FIR the verilog language code design document, and through the author timing simulation, and used for actual projects
Platform: | Size: 5541888 | Author: lirui | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code of the filter, presented here we commonly used serial FIR the verilog language code design document, and through the author timing simulation, and used for actual projects
Platform: | Size: 6000640 | Author: lirui | Hits:

[Other Embeded program] FIR32

Description: 基于DA算法的FIR带通滤波器设计，应用于FPGA实现，verilog语言描述-DA algorithm based on FIR bandpass filter design, used in FPGA implementation, verilog language to describe
Platform: | Size: 3072 | Author: Awei | Hits:

[VHDL-FPGA-Verilog] fir filter design

Description: FIR FILTER DESIGN IN VERILOG ON FPGA
Platform: | Size: 18432 | Author: GIRISH | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FIR filter in verilog for xilinx ise design suit
Platform: | Size: 190464 | Author: addy007 | Hits:

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